Senior Computer Engineering student at Iowa State University with a passion for chip design. I'm excited to apply my skills in hardware design and verification through an internship next summer.
My Resume My ProjectsI am a senior in Computer Engineering at Iowa State University, specializing in digital design and computer architecture. My current research focuses on hardware prefetching implementations to improve memory performance. As part of this work, I use FireSim, a Vivado-based FPGA simulation framework, to implement, simulate, and evaluate prefetcher designs on RISC-V cores.
I am seeking a digital design or verification internship for Summer 2026 to apply my skills in an industry environment and contribute to innovative projects.
Looking ahead, my goals are to complete a Master’s degree by May 2027. Within this time I will continue to advance research on improving memory performance. Beyond graduate study, I am eager to begin my career in computer hardware design, where I can expand my industry experience and contribute to innovative hardware solutions.
CPRE 4650: Digital design of integrated circuits employing very large scale integration (VLSI) methodologies. Technology considerations in design. High level hardware design languages, CMOS logic design styles, area-energy-delay design space characterization, datapath blocks: arithmetic and memory, architectures and systems on a chip (SOC) considerations. VLSI chip hardware design project.
CPRE 5810: Quantitative principles of computer architecture design, instruction set design, processor architecture: pipelining and superscalar design, instruction level parallelism, memory organization: cache and virtual memory systems, multiprocessor architecture, cache coherency, interconnection networks and message routing, I/O devices and peripherals.
CPRE 3810: Introduction to computer organization, evaluating performance of computer systems, instruction set design. Assembly level programming: arithmetic operations, control flow instructions, procedure calls, stack management. Processor design. Datapath and control, scalar pipelines, introduction to memory and I/O systems.
CPRE 3300: Semiconductor technology for integrated circuits. Modeling of integrated devices including diodes, BJTs, and MOSFETs. Physical layout. Circuit simulation. Digital building blocks and digital circuit synthesis. Analysis and design of analog building blocks. Laboratory exercises and design projects with CAD tools and standard cells.
CPRE 3080: Operating system concepts, processes, threads, synchronization between threads, process and thread scheduling, deadlocks, memory management, file systems, I/O systems,security, Linux-based lab experiments.
CPRE 2880: Embedded C programming. Interrupt handling. Memory mapped I/O in the context of an application. Elementary embedded design flow/methodology. Timers, scheduling, resource allocation, optimization, state machine based controllers, real time constraints within the context of an application. Applications laboratory exercises with embedded devices.
EE 2240: Mathematical preliminaries. Introduction to signals and systems. Signal manipulations. System properties. LTI systems, impulse response and convolution. Fourier Series representation and properties. Continuous and discrete-time Fourier Transforms and properties. Sampling and reconstruction. Modulation and demodulation. Applications and demonstrations using Matlab.
COMS 3090: Practical introduction to methods for managing software development. Software engineering concepts, practices and tools. Requirements analysis, structured and object-oriented design, coding, testing, and maintenance. Software process models, software tools and environments. Programming projects that provide exposure to information management techniques, client/server model, networking and communication.
Course descriptions taken from the Iowa State University Course Catalog.
Full transcript available upon request.
Designed and tested MIPS processors: Single-Cycle, 5-stage Software-Scheduled pipeline, and 5-stage Hardware-Scheduled pipeline. Final processor included full forwarding and hazard avoidance, to minimize CPI. Synthesized each processor to get timing information and compare performances.
View on GitHubProgrammed an iRobot Create 2 to navigate a warehouse environment, fully autonomously. Used Ping and IR sensors to detect and avoid obstacles, like columns, walls, and spills. Included a python GUI to activate robot and display its status, via UART communication.
View on GitHubDesigned a SpringBoot based backend for an app. Used CRUDL endpoints for communication between frontend and backend. Utilized MySQL to store and organize data into tables using one-to-one, one-to-many, many-to-many relationships. Relied on external APIs for exercises and payment processing.
View on GitHubCurrently researching hardware prefetching implementations and designing prefetchers for RISC-V cores. Developing and evaluating prefetcher designs using FireSim, a Vivado-based FPGA-accelerated cycle-accurate simulator. Created Chipyard and FireSim documentation for other researchers to use, including setup, configuration, and usage instructions.
View on GitHubPlease reach out!