Digital Design Engineer
Last Updated 06/09/2026
Researching hardware prefetching architectures to improve memory performance. Configuring prefetcher designs for RISC-V cores using the Chipyard framework. Synthesizing and evaluating prefetcher performance tradeoffs using FireSim, a Vivado-based FPGA-accelerated simulator.
Currently evaluating a prefetcher I implemented based on Pierre Michaud's Best-Offset prefetcher. It is implemented in Chipyard, simulated using FireSim, and compared against other designs. I created a prefetcher wrapper to track prefetcher accuracy, coverage, and timeliness, with the goal of prefetcher parameter exploration. My documentation for Chipyard and FireSim is available on my GitHub.
Developed a programmable 3D graphics pipeline. GPU contains a hardware rasterizer to display textured objects on a screen via VGA. Includes programmable cores for vertex shading and fragment shading, allowing for general-purpose applications. The SoC was taped-out and sent for fabrication.
We followed the full ASIC design flow: hardware architecture, RTL design, functional verification, FPGA prototyping, synthesis, PnR, and DRC/LVS checks for tapeout. My main role was cache design, where I designed a direct-mapped, write-back cache around the ChipFoundry commercial SRAM and our custom bus. Visit our website to view the design documentation and datasheet.
Designed and tested MIPS processors: Single-Cycle, 5-stage Software-Scheduled pipeline, and 5-stage Hardware-Scheduled pipeline. Final processor included full forwarding and hazard avoidance, to minimize CPI. Synthesized each processor to get timing information and compare performances.
Each component was designed structurally in VHDL, and tested using testbenches in Questa ModelSim. Over 30 MIPS instructions are supported, including arithmetic, logic, memory, and control instructions. Many test programs were written in MIPS assembly to verify processor functionality. View the full code, block diagram, and supported instructions on GitHub.
Designed a SpringBoot based backend for an app. Used CRUDL endpoints for communication between frontend and backend. Utilized MySQL to store and organize data into tables using one-to-one, one-to-many, many-to-many relationships. Relied on external APIs for exercises and payment processing.
Programmed an iRobot Create 2 to navigate a warehouse environment, fully autonomously. Used Ping and IR sensors to detect and avoid obstacles, like columns, walls, and spills. Included a python GUI to activate robot and display its status, via UART communication.
I've always been more drawn to the hardware side of computing than the software side. Taking digital logic solidified that, and since then, I was hooked on the idea of designing and implementing a processor from the ground up. My computer architecture course gave me this opportunity, and confirmed the direction I wanted to go.
I'm currently a Master of Science student at Iowa State, continuing research on hardware prefetching to improve memory performance in RISC-V cores. I am a current TA for Computer Organization and Assembly-level programming, and past TA for Digital Logic. Long term, I want to work in CPU, GPU, or NPU microarchitecture, shaping the future of processors.
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